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november 2010 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 fan4860 ? 3mhz, synchronous tinyboost? regulator fan4860 3mhz, synchronous tinyboost? regulator features ? operates with very small external components: 1 h inductor and 0402 case size input and output capacitors ? input voltage range from 2.3v to 4.5v ? fixed 3.3v or 5.0v output voltage options ? maximum load current >200ma at v in =2.3v ? maximum load current 300ma at v in =3.3v, v out =5v ? maximum load current 300ma at v in =2.7v, v out =3.3v ? up to 92% efficient ? low operating quiescent current ? true load disconnect during shutdown ? variable on-time pulse frequency modulation (pfm) with light-load power-saving mode ? internal synchronous rectifier (no external diode needed) ? thermal shutdown and overload protection ? 6-pin 2 x 2mm umlp ? 6-bump wlcsp, 0.4mm pitch applications ? usb ?on the go? 5v supply ? 5v supply ? hdmi, h-bridge motor drivers ? powering 3.3v core rails ? pdas, portable media players ? cell phones, smart phones, portable instruments description the fan4860 is a low-power boost regulator designed to provide a regulated 3.3v or 5v output from a single cell lithium or li-ion battery. output voltage options are fixed at either 3.3v or 5.0v with a guaranteed maximum load current of 200ma at v in =2.3v and 300ma at v in =3.3v. input current in shut-down mode is less than 1a, which maximizes battery life. light-load pfm operation is automatic and ?glitch-free?. the regulator maintains output regulation at no-load with as low as 37a quiescent current. the combination of built-in power transistors, synchronous rectification, and low supply current make the fan4860 ideal for battery powered applications. the fan4860 is available in 6-bump 0.4mm pitch wafer- level chip scale package (wlcsp) and a 6-lead 2x2mm ultra-thin mlp package. figure 1. typical application ordering information part number operating temperature range package packing method fan4860uc5x -40c to 85c wlcsp, 0.4mm pitch tape and reel fan4860ump5x -40c to 85c umlp-6, 2 x 2mm tape and reel FAN4860UC33X -40c to 85c wlcsp, 0.4mm pitch tape and reel please refer to tape and reel specifications at http://www.fairchildsemi.com/packaging .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 2 fan4860 ? 3mhz, synchronous tinyboost? regulator block diagrams figure 2. ic block diagram pin configuration figure 3. wlcsp (top view) figur e 4. wlcsp (bottom view) figure 5. 2x2mm umlp (top view) pin definitions pin # name description wlcsp umlp a1 6 vin input voltage . connect to li-ion battery input power source and input capacitor (c in ). b1 5 sw switching node . connect to inductor. c1 4 en enable . when this pin is high, the circuit is enabled. this pin should not be left floating. c2 3 fb feedback . output voltage sense point for v out . connect to output capacitor (c out ). b2 2 vout output voltage . this pin is both the output voltage terminal as well as an ic bias supply. a2 1, p1 gnd ground . power and signal ground reference for the ic. all voltages are measured with respect to this pin.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 3 fan4860 ? 3mhz, synchronous tinyboost? regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. units v in vin pin -0.3 5.5 v v out vout pin ?2 6 v v fb fb pin ?2 14 v v sw sw node dc -0.3 5.5 v transient: 10ns, 3mhz -1.0 6.5 v en en pin -0.3 5.5 v esd electrostatic discharge protection level human body model per jesd22-a114 2 kv charged device model per jesd22-c101 1 t j junction temperature ?40 +150 c t stg storage temperature ?65 +150 c t l lead soldering temperature, 10 seconds +260 c recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units v in supply voltage 5.0 v out 2.3 4.5 v 3.3 v out 2.5 3.2 v i out output current 200 ma t a ambient temperature ?40 +85 c t j junction temperature ?40 +125 c thermal properties junction-to-ambient thermal resistance is a function of applicat ion and board layout. this data is measured with four-layer 2s2p boards in accordance to jedec standard jesd51. specia l attention must be paid not to exceed junction temperature t j(max) at a given ambient temperate t a . symbol parameter typical units ja junction-to-ambient thermal resistance wlcsp 130 c/w umlp 57 c/w
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 4 fan4860 ? 3mhz, synchronous tinyboost? regulator electrical specifications minimum and maximum values are at v in =v en =2.3v to 4.5v (2.5 to 3.2 v in for 3.3 v out option), t a =-40c to +85c; circuit of figure 1, unless otherwise noted. typical values are at t a =25c, v in =v en =3.6v for v out =5v, and v in =v en =2.7v for v out =3.3v. symbol parameter conditions min. typ. max. units i in v in input current 5.0 v out quiescent: v in =3.6v, i out =0, en=v in 37 45 a shutdown: en=0, v in =3.6v 0.5 1.5 3.3 v out quiescent: v in =2.7v, i out =0, en=v in 50 65 shutdown: en=0, v in =2.7v 0.5 1.5 i lk_out v out leakage current v out =0, en=0, v in 3v 10 na i lk_rvsr v out to v in reverse leakage v out =5v, v in =3.6v, en=0 2.5 a v out =3.3v, v in =3v, en=0 v uvlo under-voltage lockout v in rising 2.2 2.3 v v uvlo_hys under-voltage lockout hysteresis 190 mv v enh enable high voltage 1.05 v v enl enable low voltage 0.4 v i lk_en enable input leakage current 0.01 1 a v out 5.0 v out output voltage accuracy (1) v in from 2.3v to 4.5v, i out 200ma 4.80 5.05 5.15 v v in from 2.7v to 4.5v, i out 200ma 4.85 5.05 5.15 v in from 3.3v to 4.5v, i out 300ma 4.85 5.05 5.15 3.3 v out output voltage accuracy (1) v in from 2.5v to 3.2v, i out 200ma 3.17 3.33 3.41 v ref reference accuracy referred to v out =5v 4.975 5.050 5.125 v referred to v out =3.3v 3.280 3.330 3.380 t off off time v in =3.6v, v out =5v, i out =200ma 195 240 265 ns v in =2.7v, v out =3.3v, i out =200ma 240 290 350 i out maximum output current (2) 5.0 v out v in =2.3v 200 ma v in =3.3v 300 v in =3.6v 400 3.3 v out v in =2.5v 250 v in =2.7v 300 i sw sw peak current limit 5.0 v out v in =3.6v, v out >v in 930 1100 1320 ma 3.3 v out v in =2.7v, v out >v in 650 800 950 i ss soft-start input peak current limit (2) 5.0 v out v in =3.6v, v out < v in 850 ma 3.3 v out v in =2.7v, v out < v in 700 t ss soft-start time (3) 5.0 v out v in =3.6v, i out =200ma 100 300 s 3.3 v out v in =2.7v, i out =200ma 250 750 r ds(on) n-channel boost switch v in =3.6v 300 m ? p-channel sync rectifier v in =3.6v 400 t tsd thermal shutdown i load =10ma 150 c t tsd_hys thermal shutdown hysteresis 30 c notes: 1. i load from 0 to i out ; also includes load transient response. v out measured from mid-point of output voltage ripple. effective capacitance of c out > 1.5 f. 2. guaranteed by design and characterization; not tested in production. 3. elapsed time from rising en until regulated v out.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 5 fan4860 ? 3mhz, synchronous tinyboost? regulator 5.0 v out typical characteristics unless otherwise specified, circuit per figure 1, 3.6v in , t a =25c. figure 6. efficiency vs. v in figure 7. efficiency vs. temperature, 3.6v in figure 8. line and load regulation figure 9. load regulation vs. temperature, 3.6v in figure 10. switching frequency figure 11. quiescent current 75 80 85 90 95 100 0 50 100 150 200 250 300 efficiency (%) load current (ma) 2.5 vin 3.3 vin 3.6 vin 4.5 vin 80 83 86 89 92 95 0 50 100 150 200 250 300 efficiency (%) load current (ma) -40c +25c +85c -100 -75 -50 -25 0 25 50 0 50 100 150 200 250 300 vout - 5.05v (mv) load current (ma) 2.5 vin 3.3 vin 3.6 vin 4.5 vin -100 -75 -50 -25 0 25 50 0 50 100 150 200 250 300 vout - 5.05v (mv) load current (ma) -40c +25c +85c 0 800 1600 2400 3200 4000 0 50 100 150 200 250 300 frequency (khz) load current (ma) 2.5 vin 3.6 vin 4.5 vin 25 30 35 40 45 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 quiescent current (ua) input voltage(v) -40c +25c +85c
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 6 fan4860 ? 3mhz, synchronous tinyboost? regulator 5.0 v out typical characteristics unless otherwise specified, circuit per figure 1, 3.6v in , t a =25c. figure 12. maximum dc load current figure 13. peak inductor current figure 14. output ripple, 10ma pfm load figure 15. output ripple, 200ma pwm load figure 16. 0-50ma load transient, 100ns step figure 17. 50-200ma load transient, 100ns step
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 7 fan4860 ? 3mhz, synchronous tinyboost? regulator 5.0 v out typical characteristics unless otherwise specified, circuit per figure 1, 3.6v in , t a =25c. figure 18. line transient, 5ma load, 10s step figure 19. line transient, 200ma load, 10s step figure 20. startup, no load figure 21. startup, 33 load figure 22. shutdown, 1k load figure 23. shutdown, 33 load
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 8 fan4860 ? 3mhz, synchronous tinyboost? regulator 5.0 v out typical characteristics unless otherwise specified, circuit per figure 1, 3.6v in , t a =25c. figure 24. overload protection figure 25. short-c ircuit response
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 9 fan4860 ? 3mhz, synchronous tinyboost? regulator 3.3 v out typical characteristics unless otherwise specified, circuit per figure 1, 3.0v in , t a =25c. figure 26. efficiency vs. v in figure 27. efficiency vs. temperature, 3.0v in figure 28. line and load regulation figure 29. load regulation vs. temperature, 3.0v in figure 30. quiescent current figure 31. maximum dc load current 75 80 85 90 95 100 0 50 100 150 200 250 300 efficiency (%) load current (ma) 2.5 vin 2.7 vin 3.0 vin 3.2 vin 83 86 89 92 95 98 0 50 100 150 200 250 300 efficiency (%) load current (ma) -40c +25c +85c -80 -60 -40 -20 0 20 40 0 50 100 150 200 250 300 vout - 3.33v (mv) load current (ma) 2.5 vin 2.7 vin 3.0 vin 3.2 vin -80 -60 -40 -20 0 20 40 0 50 100 150 200 250 300 vout - 3.33v (mv) load current (ma) -40c +25c +85c 30 35 40 45 50 55 2.0 2.3 2.6 2.9 3.2 3.5 quiescent current (ua) input voltage(v) -40c +25c +85c 200 300 400 500 600 700 2.0 2.3 2.6 2.9 3.2 3.5 maximum dc load current (ma) input voltage(v) -40c +25c +85c
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 10 fan4860 ? 3mhz, synchronous tinyboost? regulator 3.3 v out typical characteristics unless otherwise specified, circuit per figure 1, 3.0v in , t a =25c. figure 32. output ripple, 10ma pfm load figure 33. output ripple, 200ma pwm load figure 34. startup, no load figure 35. startup, 22 load
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 11 fan4860 ? 3mhz, synchronous tinyboost? regulator functional description circuit description fan4860 is a synchronous boost regulator, typically operating at 3mhz in continuous conduction mode (ccm), which occurs at moderate to heavy load current and low v in voltages. at light-load currents, the converter switches automatically to power-saving pfm mode. the regulator automatically and smoothly transitions between quasi-fixed-frequency continuous conduction pwm mode and variable-frequency pfm mode to maintain the highest possible efficiency over the full range of load current and input voltage. pwm mode regulation the fan4860 uses a minimum on-time and computed minimum off-time to regulate v out . the regulator achieves excellent transient response by employing current mode modulation. this technique causes the regulator output to exhibit a load line. during pwm mode, the output voltage drops slightly as the input current rises. with a constant v in , this appears as a constant output resistance. the ?droop? caused by the output resistance when a load is applied allows the regulator to respond smoothly to load transients with negligible overshoot. figure 36. output resistance ( rout ) v out as a function of i load can be computed when the regulator is in pwm mode (continuous conduction) as: load out out i r 05 . 5 v ? ? = (1) for example, at v in =3.3v, and i load =200ma, v out would drop to: v 974 . 4 2 . 0 38 . 0 05 . 5 v out = ? ? = (1a) at v in =2.3v, and i load =200ma, v out would drop to: v 914 . 4 2 . 0 68 . 0 05 . 5 v out = ? ? = (1b) pfm mode if v out > v ref when the minimum off-time has ended, the regulator enters pfm mode. boost pulses are inhibited until v out < v ref . the minimum on-time is increased to enable the output to pump up sufficiently with each pfm boost pulse. therefore, the regulator behaves like a constant on- time regulator, with the bottom of its output voltage ripple at 5.05v in pfm mode. table 1. operating states mode description invoked when: lin linear startup v in > v out ss boost soft-start v out < v reg bst boost operating mode v out =v reg shutdown and startup if en is low, all bias circuits are off and the regulator is in shutdown mode. during shutdown, true load disconnect between battery and load prevents current flow from v in to v out , as well as reverse flow from v out to v in . lin state when en rises, if v in > uvlo, the regulator first attempts to bring v out within about 1v of v in by using the internal fixed current source from v in (i lin1 ). the current is limited to about 630ma during lin1 mode. if v out reaches v in -1v during lin1 mode, the ss state is initiated. otherwise, lin1 times out after 16 clk counts and the lin2 mode is entered. in lin2 mode, the current source is incremented to 850ma. if v out fails to reach v in -1v after 64 clk counts, a fault condition is declared. ss state upon the successful completion of the lin state (v out > v in - 1v), the regulator begins switching with boost pulses current limited to about 50% of nominal level, incrementing to full scale over a period of 32 clk counts. if the output fails to achieve 90% of its setpoint within 96 clk counts at full-scale current limit, a fault condition is declared. bst state this is the normal operating mode of the regulator. the regulator uses a minimum t off -minimum t on modulation scheme. minimum t off is proportional to , which keeps the regulator?s switching fr equency reasonably constant in ccm. t on(min) is proportional to v in and is higher if the inductor current reaches 0 before t off(min) during the prior cycle. to ensure that v out does not pump significantly above the regulation point, the boost switch remains off as long as fb > v ref . 100 200 300 400 500 600 700 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output resistance (m ) input voltage (v) 3.3 vout 5.0 vout out in v v
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 12 fan4860 ? 3mhz, synchronous tinyboost? regulator fault state the regulator enters the fault state under any of the following conditions: ? v out fails to achieve the voltage required to advance from lin state to ss state. ? v out fails to achieve the voltage required to advance from ss state to bst state. ? sustained (32 clk counts) pulse-by-pulse current limit during the bst state. ? the regulator moves from bst to lin state due to a short circuit or output overload (v out < v in -1v). once a fault is triggered, the regulator stops switching and presents a high-impedance path between v in and v out . after waiting 480 clk counts, a re-start is attempted. soft-start and fault timing the soft-start timing for each state, and the fault times, are determined by the fault clock, whose period is inversely proportional to v in . this allows the regulator more time to charge larger values of c out when v in is lower. with higher v in , this also reduces power delivered to v out during each cycle in current limit. the number of clock counts for each state is illustrated in figure 37. figure 37. fault response into short circuit the fault clock period as a function of v in is shown in figure 38. figure 38. fault clock period vs. vin the v in -dependent lin mode charging current is illustrated in figure 39. figure 39. lin mode current vs. v in over-temperature protection (otp) the regulator shuts down when the thermal shutdown threshold is reached. restart, with soft-start, occurs when the ic has cooled by about 30c. over-current protection (ocp) during boost-mode operation, the fan4860 employs a cycle-by-cycle peak current limit to protect switching elements. sustained current limit, for 32 consecutive fault clk counts, initiates a fault condition. during an overload condition, as v out collapses to approximately v in -1v, the synchronous rectifier is immediately switched off and a fault condition is declared. automatic restart occurs once the overload/short is removed and the fault timer completes counting.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 13 fan4860 ? 3mhz, synchronous tinyboost? regulator application information external component selection table 2 shows the recommended external components for the fan4860: table 2. external components ref description manufacturer l1 1.0h, 0.8a, 190m , 0805 murata lqm21pn1r0mc0, or equivalent c in 2.2f, 6.3v, x5r, 0402 murata grm155r60j225m tdk c1005x5r0j225m c out 4.7f, 10v, x5r, 0603 (4) kemet c0603c475k8pac tdk c1608x5r1a475k note: 4. a 6.3v-rated 0603 capacitor may be used for c out , such as murata grm188r60j225m. all datasheet parameters are valid with the 6.3v-rated capacitor. due to dc bias effects, the 10v capacitor offers a performance enhancement; particularly output ripple and transient response, without any size increase. output capacitance (c out ) stability the effective capacitance (c eff ) of small, high-value, ceramic capacitors decrease as their bias voltage increases, as shown in figure 40. figure 40. c eff for 4.7 f, 0603, x5r, 6.3v (murata grm188r60j475k) fan4860 is guaranteed for stable operation with the minimum value of c eff (c eff(min) ) outlined in table 3. table 3. minimum c eff required for stability operating conditions c eff(min) ( f) v in (v) i load (ma) 2.3 to 4.5 0 to 200 1.5 2.7 to 4.5 0 to 200 1.0 2.3 to 4.5 0 to 150 1.0 c eff varies with manufacturer, dielectric material, case size, and temperature. some manufacturers may be able to provide an x5r capacitor in 0402 case size that retains c eff >1.5 f with 5v bias; others may not. if this c eff cannot be economically obtained and 0402 case size is required, the ic can work with the 0402 capacitor as long as the minimum v in is restricted to >2.7v. for best performance, a 10v-rated 0603 output capacitor is recommended (kemet c0603c475k8pac, or equivalent). since it retains greater c eff under bias and over temperature, ouptut ripple can is reduced and transient capability enhanced. output voltage ripple output voltage ripple is inversely proportional to c out . during t on , when the boost switch is on, all load current is supplied by c out . out load on ) p p ( ripple c i t v ? = ? and (2) ? ? ? ? ? ? ? ? ? ? = ? = out in sw sw on v v 1 t d t t therefore: (3) out load out in sw ) p p ( ripple c i v v 1 t v ? ? ? ? ? ? ? ? ? ? ? = ? (4) where: sw sw f 1 t = (5) as can be seen from equation 4, the maximum v ripple occurs when v in is minimum and i load is maximum. startup input current limiting is in effect during soft-start, which limits the current available to charge c out . if the output fails to achieve regulation within the time period described in the soft-start section above; a fault occurs, causing the circuit to shut down, then restart after a significant time period. if c out is a very high value, the circuit may not start on the first attempt, but eventually achieves regulation if no load is present. if a high-current load and high capacitance are both present during soft-start, the circuit may fail to achieve
? 2010 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1.1.0 14 fan4860 ? 3mhz, synchronous tinyboost? regulator regulation and continually attempt soft-start, only to have c out discharged by the load when in the fault state. the circuit can start with higher values of c out under full load if v in is higher, since: out in ripple ) pk ( lim out v v 2 i i i ? ? ? ? ? ? ? ? = ( 6) generally, the limitation occurs in bst mode. the fan4860 starts on the first pass (without triggering a fault) under the following conditions for c eff(max) : table 4. maximum c eff for first-pass startup operating conditions c eff(max) ( f) v in (v) r load(min) 5.0 v out 3.3 v out > 2.3 25 ? 16 ? 10 > 2.7 25 ? 16 ? 15 > 2.7 33 ? 20 ? 22 c eff values shown in table 4 typically apply to the lowest v in . the presence of higher v in enhances ability to start into larger c eff at full load. transient protection to protect against external voltage transients caused by esd discharge events, or improper external connections, some applications employ an external transient voltage suppressor (tvs) and schottky diode (d1 in figure 41). figure 41. fan4860 with external transient protection the tvs is designed to clamp the fb line (system v out ) to +10v or ?2v during external transient events. the schottky diode protects the output devices from the positive excursion. the fb pin can tolerate up to 14v of positive excursion, while both the fb and vout pins can tolerate negative voltages. the fan4860 includes a circuit to detect a missing or defective d1 by comparing v out to fb. if v out ? fb > about 0.7v, the ic shuts down. the ic remains shut down until v out < uvlo and v in < uvlo+0.7 or en is toggled. c out2 may be necessary to preserve load transient response when the schottky is used. when a load is applied at the fb pin, the forward voltage of the d1 rapidly increases before the regulator can respond or the inductor current can change. this causes an immediate drop of up to 300mv, depending on d1?s characteristics if c out2 is absent. c out2 supplies instantaneous current to the load while the regulator adjusts the inductor current. a value of at least half of the minimum value of c out should be used for c out2 . c out2 needs to withstand the maximum voltage at the fb pin as the tvs is clamping. the maximum dc output current available is reduced with this circuit, due to the additional dissipation of d1. layout guideline figure 42. wlcsp suggested layout (top view) figure 43. umlp suggested layout (top view)
? 20 1 0 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1. 1. 0 15 fan4860 ? 3mhz, synchronous tinyboost? regulator physical dimensions figure 44. 6-lead, 0.4mm pitch, wlcsp package product-specific dimensions product d e x y fan4860uc5x 1.230mm +/-0.030mm 0.880mm +/-0.030mm 0.240mm 0.215mm FAN4860UC33X package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or o btain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . seating plane 0.06 c 0.05 c c side views notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerances per asmey14.5m, 1994. d. datum c, the seating plane is defined by the spherical crowns of the balls. e. package typical height is 586 microns 39 microns (547-625 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filename: uc006acrev4. bottom view top view recommended land pattern (nsmd pad type) e d b a ball a1 index area a1 0.03 c 2x 0.03 c 2x 0.2080.021 0.3780.018 1 2 a b c 0.40 0.40 0.005 cab (x) +/-0.018 (y) +/-0.018 ?0.2600.010 0.40 6x e d f f 0.40 (?0.20) cu pad (?0.30) solder mask opening f 0.625 0.547
? 20 1 0 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1. 1. 0 16 fan4860 ? 3mhz, synchronous tinyboost? regulator physical dimensions figure 45. 6-lead umlp package package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or o btain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . side view notes: a. package conforms to jedec mo-229 except where noted. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. landpattern recommendation is based on fsc design only. e. drawing filename: mkt-umlp06erev2. bottom view top view recommended land pattern 1 3 6 4 2x 2x 0.05 0.00 0.55 max 0.10 c 0.08 c (0.15) c seating plane 2.0 2.0 0.70 0.80 1.35 1.45 pin1 ident 0.10 c a b 0.05 c 6x 6x 0.10 c 0.10 c pin1 ident a b 0.35 0.25 0.35 0.25 0.65 1.45 0.80 0.50 0.35 0.65 6x 6x 1.80 a (0.25)
? 20 1 0 fairchild semiconductor corporation www.fairchildsemi.com fan4860 ? rev. 1. 1.0 17 fan4860 ? 3mhz, synchronous tinyboost? regulator

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